Antingen stödjer din webbläsare inte javascript, eller är javascript inaktiverat. Denna webbplats fungerar bäst om du aktiverar javascript.

Andreas de Blanche

Universitetslektor

Anställd på Avdelningen för matematik, data och lantmäteri.

Forskar inom området teknik, elektroteknik och elektronik.


Research area/research interest

Andreas de Blanche is a senior lecturer in computer engineering at University West. His research deals with computer simulations and how hardware and scheduling can best be used to suit the requirements of various programs. Andreas focus, however, lies mostly on the area of industrial simulations.
Today, industrial companies are making more and more use of simulations when developing new products, instead of, or in addition to, physical testing. A new design for an aircraft engine, for example, can be tested virtually instead of in a real aircraft, which could actually crash. Another example is carrying out virtual testing on new car models instead of physically crashing them. These simulations require large amounts of computing power, and can take weeks to carry out.
Different simulation programs require computers to have different amounts of processor capacity, memory capacity and network capacity.

If there is insufficient capacity in some respect, a bottleneck occurs which slows down the entire simulation. More effective use could be made of companies' resources and the time taken to develop new products could be shortened if it were possible to tailor computing resources according to the needs of different simulation programs. Andreas de Blanche's research is based on developing methods for being better able to assess how computing resources for different simulation programs should be combined, i.e. co-scheduled.

Teaching/supervision

Andreas de Blanche is mainly teaching courses in computer architecture, operating systems and network technology. He is also a supervisor and examiner for University- and Bachelor thesis degree projects.

Nyckelord

Computer science, computer engineering, operating systems, high performance computing, co-scheduling, industrial simulations, network technology

Publikationer


A methodology for estimating co-scheduling slowdowns due to memory bus contention on multicore nodes

Publicerat

A methodology for estimating co-scheduling slowdowns due to memory bus contention on multicore nodes

When two or more programs are co-scheduled on the same multicore computer they might experience a slowdown due to the limited off-chip memory...

A Slowdown Prediction Method to Improve Memory Aware Scheduling

Publicerat

A Slowdown Prediction Method to Improve Memory Aware Scheduling

Scientific and technological advances in the area of integrated circuits have allowed the performance of microprocessors to grow exponentially sinc...

A Tool for Processor Dependency Characterization of HPC Applications

Publicerat

A Tool for Processor Dependency Characterization of HPC Applications

In this paper we have implemented and verified Cpugen, a tool for characterization of processor resource utilization of HPC applications .Toward th...

Addressing characterization methods for memory contention aware co-scheduling

Publicerat

Addressing characterization methods for memory contention aware co-scheduling

The ability to precisely predict how memory contention degrades performance when co-scheduling programs is critical for reaching high performance...

Availability of Unused Computational Resources in an Ordinary Office Environment

Publicerat

Availability of Unused Computational Resources in an Ordinary Office Environment

The study presented in this paper highlights an important issue that was subject for discussionsand research about a decade ago and now have gained...

Disallowing Same-program Co-schedules to Improve Efficiency in Quad-core Servers

Publicerat

Disallowing Same-program Co-schedules to Improve Efficiency in Quad-core Servers

Programs running on different cores in a multicore serverare often forced to share resources like off-chip memory,caches, I/O devices, etc. This...

Exhausted Dominated Performance : Basic Proof of Concept

Publicerat

Exhausted Dominated Performance : Basic Proof of Concept

Exhaustion dominated performance : a first attempt

Publicerat

Exhaustion dominated performance : a first attempt

In this paper we present a first attempt to an analytical method to discover and understand how the available resources influence the execution tim...

Exhaustion dominated performance : an empirical method evalutation

Publicerat

Exhaustion dominated performance : an empirical method evalutation

Flipping the Data Center Network : Increasing East-West Capacity Using Existing Hardware

Publicerat

Flipping the Data Center Network : Increasing East-West Capacity Using Existing Hardware

In today's datacenters, there is an increasing demand for more network traffic capacity. The majority of the increase in traffic is internal to the...

Increasing Throughput of Multiprogram HPC Workloads : Evaluating a SMT Co-Scheduling Approach

Publicerat

Increasing Throughput of Multiprogram HPC Workloads : Evaluating a SMT Co-Scheduling Approach

Simultaneous Multithreading (SMT) is a technique that allows formore efficient processor utilization by scheduling multiple threadson a single...

Initial Formulation of Why Disallowing Same Program Co-schedules Improves Performance

Publicerat

Initial Formulation of Why Disallowing Same Program Co-schedules Improves Performance

Co-scheduling processes on different cores in the same server might leadto excessive slowdowns if they use the same shared resource, like a memory...

Integration and Optimization of a 64-core HPC for FEM- and/or CFD Welding Simulations

Publicerat

Integration and Optimization of a 64-core HPC for FEM- and/or CFD Welding Simulations

Method for Experimental Measurement of an Applications Memory Bus Usage

Publicerat

Method for Experimental Measurement of an Applications Memory Bus Usage

The disproportion between processor and memory bus capacities has increased constantly during the last decades. With the introduction of multi-core...

Minimizing Total Cost ($$) and Maximizing Throughput : A Metric for Node versus Core Usage in Multi-Core Clusters

Publicerat

Minimizing Total Cost ($$) and Maximizing Throughput : A Metric for Node versus Core Usage in Multi-Core Clusters

When most commercial clusters had one processor core each, decreasing the runtime meant executing the application over more nodes – the associated...

Multicore Clusters for CFD Simulations : Comparative Study of Three CFD-Softwares

Publicerat

Multicore Clusters for CFD Simulations : Comparative Study of Three CFD-Softwares

Multicore processors have come to stay, fulfill Moore’s law and might very well revolutionize the computer industry. However, we are now in a...

Node Sharing for Increased Throughput and Shorter Runtimes : an Industrial Co-Scheduling Case Study

Publicerat

Node Sharing for Increased Throughput and Shorter Runtimes : an Industrial Co-Scheduling Case Study

The allocation of jobs to nodes and cores in industrial clusters is often based on queue-system standard settings, guesses or perceived fairness...

Operativsystem : teori och praktiskt handhavande

Publicerat

Operativsystem : teori och praktiskt handhavande

Terrible Twins : A Simple Scheme to Avoid Bad Co-Schedule

Publicerat

Terrible Twins : A Simple Scheme to Avoid Bad Co-Schedule

Co-scheduling processes on different cores in the same server might lead to excessive slowdowns if they use a shared resource,like the memory bus. ...

Thing-to-thing electricity micro payments using blockchain technology

Publicerat

Thing-to-thing electricity micro payments using blockchain technology

Thing-to-thing payments are a key enabler in the Internet of Things (IoT) era, to ubiquitously allow for devices to pay each other for services...